With recent enhancements in the speed and performance of semiconductor integrated circuit devices (IC chips) used in microprocessors of computers and the like, the number of terminals tends to increase, and the pitch between terminals tends to decrease accordingly. In general, a plurality of terminals is densely arranged in an array on the bottom surface of an IC chip and the terminal group is connected to the terminal group of a motherboard in a “flip chip” manner. However, since the terminal group of the IC chip and the terminal group of the motherboard are substantially different to each other with respect to the pitch between the terminals, a method for manufacturing a package in which the IC chip is mounted on an IC chip mounting circuit board and the package is mounted on the motherboard is employed. In a wiring board constituting such a package, it is proposed to employ a built-in capacitor in order to reduce the switching noise of the IC chip or the like. As an example of such a wiring board, a wiring board in which a capacitor is accommodated in an accommodation hole of a core board made of polymer material, and a buildup layer is formed on top and rear surfaces of the core board is disclosed in, e.g., Japanese Patent Application Laid-Open (kokai) No. 2005-39243.
More particularly, the wiring board according to the above-identified application has an accommodation hole that opens at an upper surface and a lower surface in the center of a core board, and a via array type ceramic capacitor is accommodated in the accommodation hole.
FIG. 15 shows an example of a conventional (prior art) via array type ceramic capacitor 201. This ceramic capacitor 201 is comprised of a capacitor forming layer portion 202, a cover layer portion 203 and an interlayer portion 204. The capacitor forming layer portion 202 has a laminated structure in which a plurality of first inner electrodes 206 and a plurality of second inner electrodes 207 are each alternately laminated by sandwiching a ceramic dielectric layer 205 therebetween. The ceramic dielectric layer 205 is made of a sintered body of barium titanate, which is a high dielectric constant ceramic, and functions as a dielectric (insulator) between the first inner electrode 206 and the second inner electrode 207.
The interlayer portion 204 is comprised of a plurality of laminated ceramic dielectric layers 208, and is arranged between the capacitor forming layer portions 202. In the capacitor forming layer portion 202, there is a portion where the first inner electrode 206 overlaps the second inner electrode 207 in a thickness direction, and a portion where the first inner electrode 206 does not overlap the second inner electrode 207. Thus, although there is a difference in thickness (due to the formation of electrodes) in the capacitor forming layer portion 202 due to formation of the inner electrodes 206, 207, the difference in thickness can be compensated by providing the interlayer portion 204 between the capacitor forming layer portions 202.
Similar to the interlayer portion 204, the cover layer portion 203 has a structure in which a plurality of ceramic dielectric layers 209 is laminated and disposed on a surface portion of the capacitor 201 so as to cover the capacitor forming layer portion 202. By forming the cover layer portion 203, the insulation, heat resistance, moisture resistance and the like of the capacitor 201 are maintained.
A plurality of via holes 210 is formed in the ceramic capacitor 201. These via holes 210 penetrate the capacitor 201 in the thickness direction, i.e., extend transversely of capacitor 201 rather than extending longitudinally, and are disposed in a lattice pattern (i.e., in the form of array) over the whole surface of the capacitor 201. First and second via conductors are indicated at 211 and 212, and a via conductor (211 or 212) penetrating between an upper surface and a lower surface of the capacitor 201 is formed in each via hole 210. Each first via conductor 211 penetrates each first inner electrode 206 so that the first inner electrodes 206 are electrically connected to each other. Each second via conductor 212 penetrates each second inner electrode 207 so that the second inner electrodes 207 are electrically connected to each other.
The thus-constituted ceramic capacitor 201 is produced, for example, using the following procedures. First, a nickel paste for the inner electrode is screen-printed to a ceramic green sheet and is allowed to dry. Then, a plurality of green sheets is laminated and compressed in a laminate direction to integrate each green sheet whereby a green sheet laminated body is formed. Further, a plurality of via holes 210 is formed in the green sheet laminated body, and a nickel paste for via conductor is filled in each via hole 210. Thereafter, the green sheet laminated body is degreased and fired at a predetermined temperature for a predetermined period to thereby complete the ceramic capacitor 201.
As disclosed in the above-identified application, the ceramic capacitor 201 in FIG. 15 is used as a built-in capacitor. However, it can also be used as a surface-mounted capacitor on a wiring board.
When a conventional ceramic capacitor 201 shown in FIG. 15 is built in to a wiring board as disclosed in the above-identified application, it has been confirmed that a Vickers examination indicates a residual stress remaining near the surface of the capacitor 201. That is, when a compression stress is applied to in a first direction (i.e., a XY direction) perpendicular to a thickness direction (the Z direction) of the capacitor 201, a tensile stress is exerted in the thickness direction. When embedding the ceramic capacitor 201 in the wiring board, the ceramic capacitor 201 is pulled in the Z direction due to contraction of a buildup layer formed on the cover layer portion 203. The cover layer portion 203 of the ceramic capacitor 201 is only comprised of ceramic dielectric layers 209 and has a relatively low toughness, i.e., is relatively weak. Thus, a crack 215 (refer to FIG. 16) is generated or produced near each via conductor 211, 212 in the cover layer portion 203. As a result, the reliability of the wiring board deteriorates.
Further, as shown in FIG. 17, when the ceramic capacitor 201 is surface-mounted on a wiring board 220 by a flip-chip method, compression stress (i.e., stress in X and Y directions) is produced near the surface of the ceramic capacitor 201 due to a difference in thermal expansion between the wiring board 220 and the ceramic capacitor 201. Therefore, the ceramic capacitor 201 is cambered or bowed, and cracking is likely to occur in the cover layer portion 203.
More particularly, as shown in FIG. 18, when a cambered ceramic capacitor 201 is surface-mounted on the wiring board 220, a further large stress is produced near the surface of the ceramic capacitor 201. As a result, the ceramic capacitor 201 is likely to deform, and there is a high possibility of cracking occurring in the ceramic capacitor 201.
Further, as shown in FIG. 19, when the ceramic capacitor 201 is surface-mounted on the wiring board 220 and a gap between the wiring board 220 and the ceramic capacitor 201 is sealed by an underfill material 230, a tensile stress (in the direction Z) due to a thermosetting contraction of the underfill material 230 is exerted on the ceramic capacitor 201. As a result, cracking is likely to occur in the cover layer portion 203 of the ceramic capacitor 201.